In the field of PCB design, electromagnetic compatibility (EMC) directly determines the stability and reliability of electronic products. Poor EMC performance may lead to signal interference, equipment malfunctions, or even failure to meet industry certification standards. Among all factors affecting EMC, PCB routing is a core link that can be optimized through design strategies. This article will conduct a comprehensive analysis from basic wiring rules to advanced grounding handling, providing practical solutions for engineers to improve EMC performance during the routing phase.

1. The Core Relationship Between PCB Routing and EMC: Why Routing Decides EMC Performance

Before discussing specific routing methods, it is necessary to clarify the intrinsic connection between routing and EMC. Electromagnetic interference (EMI) in PCBs mainly comes from two aspects: radiated emission (the board generates electromagnetic waves that interfere with external devices) and radiated susceptibility (the board is affected by external electromagnetic fields). Both are closely related to the physical characteristics of the routing:

Signal loop area: The larger the loop formed by the signal line and its return path (such as ground or power line), the stronger the radiated emission and the higher the susceptibility to external interference. For example, a 10cm-long signal line with a 5cm spacing from the ground line will form a loop area of 50cm², which is 10 times more likely to generate EMI than a loop area of 5cm².

Routing topology: Star topology is more EMC-friendly than daisy-chain topology for multi-load signal lines. Taking a DDR3 memory bus as an example, daisy-chain routing may cause signal reflections and crosstalk between adjacent lines, while star topology ensures that each branch has the same length, reducing impedance mismatch and EMI.

Component placement and routing path: Long parallel routing of high-speed signals (such as clock signals above 100MHz) and sensitive signals (such as analog sensor signals) will cause capacitive and inductive coupling, leading to crosstalk. Tests show that when the parallel length of two signal lines exceeds 5cm and the spacing is less than 0.2mm, the crosstalk amplitude can reach more than 20% of the signal amplitude, seriously affecting EMC.

2. EMC-Oriented PCB Routing Rules: From Basic Specifications to Advanced Optimization

2.1 Basic Routing Rules to Reduce EMI

Minimize signal loop area: For all signal lines, especially high-current and high-speed signals, ensure that the signal line and its return path (ground/power line) are as close as possible. For example, when routing a 5V/2A power line, the power line and ground line should be placed in parallel with a spacing of less than 0.5mm, and the length difference should not exceed 10% of the total length, thereby reducing the loop area and suppressing radiated emission.

Control line impedance and matching: Impedance mismatch is one of the main causes of signal reflection, and reflected signals will generate additional EMI. For high-speed signals (such as USB 3.0, HDMI), the characteristic impedance of the routing should be strictly controlled (usually 50Ω for single-ended lines and 90Ω for differential pairs). During routing, use impedance calculation tools (such as Altium Designer's Impedance Calculator) to determine parameters such as line width, line spacing, and dielectric thickness. For example, in a 4-layer PCB with a dielectric constant of 4.4, a single-ended line with a characteristic impedance of 50Ω requires a line width of 0.3mm when the dielectric thickness between the signal layer and the ground layer is 0.2mm.

Avoid stubs and redundant routing: Stubs (unused branch lines) will cause signal reflections and resonance, especially in high-frequency circuits. For example, a stub with a length of 1/4 of the signal wavelength will form a short circuit at the stub end, leading to severe EMI. Therefore, during routing, stubs should be avoided as much as possible; if they cannot be avoided, the length should be controlled to less than 1/20 of the signal wavelength (e.g., for a 1GHz signal, the stub length should be less than 7.5mm).

2.2 Differential Pair Routing Rules for EMC Enhancement

Differential signals (such as Ethernet, PCIe) rely on the mutual cancellation of electromagnetic fields between two lines to reduce EMI, so their routing has strict requirements:

Equal length and equal spacing: The length difference between the two lines of the differential pair should be less than 5mm (for signals above 1GHz, less than 2mm) to avoid skew (time delay difference) and ensure that the signals arrive at the receiver simultaneously. The spacing between the two lines should be kept consistent throughout the routing path (usually 0.2-0.5mm) to maintain stable differential impedance.

Avoid crossing splits and vias: Crossing ground or power splits will break the return path of the differential pair, leading to increased EMI. Vias will introduce additional inductance and capacitance, affecting signal integrity and EMC. If vias must be used (e.g., layer changes), the number should be controlled to no more than 2 per line, and the two lines of the differential pair should pass through vias at the same position to minimize length difference.

Shielding and isolation: For high-speed differential pairs (such as PCIe 4.0), a ground line can be placed on both sides of the differential pair (with a spacing of 0.3-0.5mm from the differential pair) for shielding. This can reduce crosstalk between the differential pair and adjacent signal lines by more than 30%, while suppressing radiated emission.