In high-speed PCB design (e.g., signals above 5Gbps), PCB Route is no longer just a "wiring connection" task—signal integrity (SI) issues (such as reflection, crosstalk) and timing violations caused by improper routing can directly lead to system crashes or performance degradation. Pre-layout route simulation and analysis, as a key link between schematic design and physical routing, can identify potential risks in advance (reducing post-routing modification costs by 60%-80%). This article takes mainstream EDA tools (Altium Designer, Cadence Allegro) as examples to detail the step-by-step process of SI simulation, timing analysis, and pre-layout route verification, focusing on parameter setting specifications, result judgment criteria, and optimization directions, to provide a practical guide for high-reliability PCB Route design.

1. Signal Integrity (SI) Simulation: Predict and Resolve High-Speed Signal Anomalies

Signal Integrity (SI) simulation focuses on analyzing whether the signal waveform, amplitude, and noise margin meet the standard during transmission (e.g., PCIe 4.0, DDR5 signals) to avoid issues such as overshoot, undershoot, reflection, and crosstalk. The simulation process is divided into "preparation", "model building", "simulation execution", and "result analysis & optimization" four stages.

1.1 Preparation: Confirm Simulation Scope and Tool Selection

Define Simulation Objects: Prioritize high-speed signals with strict SI requirements, such as:

Serial differential signals: PCIe (4.0/5.0), USB4, Ethernet (10G/25G BASE-T);

Parallel bus signals: DDR5/DDR6 (data/address/control signals);

High-frequency clock signals: 100MHz+ clock (e.g., CPU core clock, PLL output clock).

Avoid including low-speed signals (e.g., UART, I2C,<10MHz) in SI simulation to reduce unnecessary workload.

Tool Matching:

For medium-speed designs (≤10Gbps, e.g., industrial control PCBs): Use built-in SI simulators in Altium Designer (e.g., Signal Integrity Analyzer), which supports quick model calling and waveform comparison without complex environment configuration;

For high-speed designs (>10Gbps, e.g., server/communication PCBs): Use professional tools such as Cadence Sigrity PowerSI or Keysight ADS, which provide more accurate 3D field simulation capabilities (supporting lossy transmission line modeling, electromagnetic coupling analysis) to handle complex SI issues (e.g., multi-line crosstalk in dense wiring).

1.2 Model Building: Establish Accurate Component and Transmission Line Models

Component Model Import:

Active components (ICs, FPGAs): Import IBIS models (preferred for SI simulation) or SPICE models provided by manufacturers. For example, when simulating DDR5 memory, import the IBIS model of the memory controller (e.g., Intel Xeon CPU) and memory 颗粒 (e.g., Samsung K4A8G165WB-BCRC), ensuring the model version matches the component (e.g., IBIS 5.0 for DDR5). Key parameters to check:

Input/output buffer voltage (VOH/VOL) compliance with the protocol (e.g., DDR5 VOH=1.1V±5%);

Rising/falling edge time (tr/tf, typically 10%-90% of the waveform, requiring ≤20ps for 25Gbps signals);

Passive components (connectors, resistors): Use manufacturer-provided S-parameter models (for high-frequency signals >10Gbps) or simplified RLC models (for low-frequency signals<5Gbps). For example, a PCIe 5.0 connector’s S-parameter model (up to 40GHz) should be imported to simulate insertion loss (IL ≤3dB at 20GHz) and return loss (RL ≥15dB at 20GHz).

Transmission Line Model Definition:

Pre-layout simulation: Since the actual routing is not completed, define the transmission line based on the planned stack-up (e.g., 8-layer PCB: Signal1-GND1-Signal2-Power1-Signal3-GND2-Signal4-Power2). Key parameters:

Impedance: Set according to the signal protocol (e.g., PCIe 5.0 differential impedance 85Ω±10%, DDR5 single-ended impedance 50Ω±10%);

Dielectric constant (εr): Based on the PCB substrate material (e.g., FR-4 εr=4.2±0.2 at 1GHz, Rogers 4350 εr=3.48±0.05);

Loss model: Include conductor loss (skin effect) and dielectric loss (tanδ), e.g., FR-4 tanδ=0.02 at 1GHz, which is critical for simulating signal attenuation at high frequencies (e.g., 25Gbps signals attenuate by 0.5dB/inch on FR-4).

1.3 Simulation Execution: Configure Test Scenarios and Run Simulations

Test Scenario Setting:

Single-line simulation (for reflection analysis): Simulate the signal transmission from the transmitter to the receiver, set the drive voltage (e.g., 1.8V for DDR5), and add termination resistors (e.g., parallel 50Ω at the receiver end for DDR5) to observe whether there is reflection (reflection coefficient ρ ≤5% is qualified);

Multi-line simulation (for crosstalk analysis): Select adjacent signal lines (e.g., 4 DDR5 data lines with a spacing of 5mil), set the "aggressor line" (driven line) and "victim line" (undriven line), simulate the crosstalk amplitude (crosstalk noise ≤10% of the signal amplitude is qualified), and check whether the crosstalk exceeds the protocol limit (e.g., DDR5 crosstalk margin ≥200mV);

Timing simulation (synchronous with timing analysis): Simulate the signal arrival time at the receiver end to check whether it meets the setup/hold time requirements (e.g., DDR5 setup time tSU ≥15ps, hold time tH ≥5ps).

Simulation Run:

In Altium Designer: After importing models and defining transmission lines, use the "Run SI Simulation" function to generate time-domain waveforms (waveform duration typically 10-20 signal cycles, e.g., 10 cycles for a 1GHz signal, duration 10ns);

In Cadence Sigrity: Use "Quick Eye" to generate eye diagrams (a key indicator of SI performance), set the sampling rate (≥5x the signal bandwidth, e.g., 125GSa/s for 25Gbps signals), and run the simulation to observe the eye opening (eye height ≥0.3V, eye width ≥50ps is qualified for PCIe 4.0).