Power supply circuits are the "energy backbone" of electronic devices—whether for consumer electronics (e.g., smartphones, laptops) or industrial equipment (e.g., EV chargers, PLCs). Their PCB routing directly impacts device stability: excessive voltage drop causes underpowered components (e.g., microcontrollers resetting), thermal hotspots lead to component overheating (reducing lifespan by 50%+), and EMI interference disrupts sensitive signals (e.g., sensor data, radio communications).

Unlike signal circuits (which prioritize signal integrity), power supply PCB routing focuses on current-carrying capacity, heat dissipation, and electromagnetic compatibility (EMC). This article systematically outlines core layout rules tailored to three key challenges—voltage drop, thermal hotspots, and EMI interference—with actionable guidelines, calculation formulas, and real-world examples to ensure reliable power delivery.

1. Routing Rules to Minimize Voltage Drop: Ensuring Stable Power Delivery

Voltage drop (ΔV) in power traces occurs due to trace resistance (R = ρL/A, where ρ = copper resistivity, L = trace length, A = cross-sectional area). For power circuits (especially those carrying high currents, e.g., 1A+), even small voltage drops (e.g., >0.5V for 5V supplies) can destabilize loads. The goal is to design traces with low resistance to keep ΔV within acceptable limits (typically ≤3% of the supply voltage).

1.1 Core Routing Rules

Rule 1: Calculate Trace Width Based on Current and Voltage Drop Requirements

Trace width directly determines cross-sectional area (A) and resistance—wider traces reduce resistance and voltage drop. Use the IPC-2221 standard (the industry benchmark for PCB trace current-carrying capacity) or the following formula to calculate minimum width:

W (mm) = (I × L) / (ΔV × σ × t)

I = Maximum current (A);

L = Trace length (mm);

ΔV = Allowable voltage drop (V, e.g., 0.1V for 12V supplies);

σ = Copper conductivity (58 S/m × 10⁶, at 25°C);

t = Copper thickness (mm, typically 0.035mm for 1oz copper, 0.07mm for 2oz).

Example: For a 12V power trace carrying 3A, length 100mm, allowable ΔV 0.3V (2.5% of 12V), 1oz copper (t=0.035mm):

W = (3 × 100) / (0.3 × 58×10⁶ × 0.035) ≈ 0.5mm.

Practical adjustment: Add 20% margin (W=0.6mm) to account for temperature rise (copper resistance increases with heat).

Rule 2: Minimize Trace Length (Shorten Power Paths)

Trace resistance is proportional to length—longer traces = higher resistance = greater voltage drop.

Route power traces directly from the source (e.g., voltage regulator, battery connector) to the load (e.g., IC, motor); avoid detours around other components.

For multi-load circuits (e.g., a 5V rail powering a microcontroller and sensors), use a "star topology" (each load connects directly to the power source via separate traces) instead of a "daisy chain" (loads connected in series along one trace). Daisy chains cause cumulative voltage drop—e.g., a 1A, 100mm trace powering two sensors may have 0.2V drop at the first sensor and 0.4V at the second, while a star topology keeps drop at 0.2V for both.

Rule 3: Use Thicker Copper for High-Current Traces

Increasing copper thickness (e.g., from 1oz to 2oz) doubles cross-sectional area, halving resistance and voltage drop.

For high-current circuits (e.g., EV charger power rails, 10A+), specify 2oz–4oz copper.

If board thickness is limited (e.g., consumer electronics), use parallel traces (two identical traces routing side-by-side) to double effective area. For example, two 0.8mm-wide, 1oz traces carry the same current as one 1.6mm-wide, 1oz trace—ideal for narrow PCB spaces.

1.2 Verification: Test Voltage Drop Post-Layout

Use PCB design software (e.g., Altium Designer, KiCad) to simulate voltage drop:

Mark the power source and key loads;

Run a "voltage drop analysis" to check ΔV at each load—ensure no point exceeds the 3% limit;

Adjust trace width/length for areas with excessive drop (e.g., widen a 0.5mm trace to 0.8mm if ΔV=0.4V for a 12V supply).

2. Routing Rules to Avoid Thermal Hotspots: Enhancing Heat Dissipation

Power traces generate heat due to Joule heating (P = I²R). If heat cannot dissipate, trace temperature rises—exceeding 105°C (typical copper melting point for PCB traces) causes trace delamination (from the substrate) or even burnout. Thermal hotspots also spread to nearby components (e.g., capacitors, ICs), reducing their lifespan. Routing rules for heat dissipation focus on maximizing heat transfer to the environment or heat sinks.

2.1 Core Routing Rules

Rule 1: Widen Traces to Reduce Current Density

Current density (J = I/A, measured in A/mm²) is the primary driver of heat generation—lower J = less heat. The IPC-2221 standard recommends maximum current density of 10–15 A/mm² for short-term pulses (e.g., 1s) and 5–8 A/mm² for continuous operation.

For continuous 5A current: A = I/J = 5/6 ≈ 0.83 mm² (1oz copper: 0.035mm thick → width = 0.83 / 0.035 ≈ 23.7mm—impractical for small PCBs). Instead, use copper pours (large, solid copper areas) for high-current rails—e.g., a 50mm×10mm copper pour (1oz) has A=50×10×0.035=17.5mm², J=5/17.5≈0.29 A/mm² (well within limits).

Rule 2: Use Copper Pours and Thermal Vias for Heat Spread

Copper pours act as "heat spreaders," distributing heat over a large area instead of concentrating it in narrow traces.

For power components (e.g., voltage regulators, MOSFETs), connect their power pins to a solid copper pour (not narrow traces). For example, a linear regulator (e.g., LM1117) dissipating 1W should be connected to a 30mm×20mm copper pour (1oz) to keep temperature below 80°C.

Add thermal vias (vias with large copper pads) to link top and bottom copper pours—vias transfer heat from the top layer (where components are mounted) to the bottom layer (exposed to air). Use 4–8 thermal vias (0.6mm drill size, 1.2mm pad size) around high-heat components; space vias 2–3mm apart for optimal heat transfer.

Rule 3: Avoid Trace Constrictions (Necking)

Trace constrictions (narrow sections in an otherwise wide trace) create localized high current density and hotspots.

Never reduce trace width at component pads (e.g., a 2mm-wide trace narrowing to 0.5mm at a resistor pad)—this causes J to spike from 2 A/mm² to 8 A/mm², generating a hotspot.

If a narrow trace is unavoidable (e.g., to fit between pads), limit its length to ≤5mm and widen it immediately after the pad to restore current density.

2.2 Verification: Thermal Simulation

Use thermal analysis tools (e.g., ANSYS Icepak, Altium Thermal Analyzer) to:

Simulate steady-state temperature of power traces and components;

Identify hotspots (temperature >85°C for consumer electronics, >100°C for industrial);

Add copper pours/thermal vias to hotspots until temperatures are within safe limits.

3. Routing Rules to Suppress EMI Interference: Ensuring EMC Compliance

Power supply circuits (especially switching regulators, e.g., buck converters) generate high-frequency noise (100kHz–100MHz) that propagates through traces as electromagnetic radiation (EMI) or conducted noise. This interferes with sensitive circuits (e.g., RF modules, analog sensors), causing signal distortion or device malfunctions. Routing rules for EMI focus on minimizing noise generation and containing noise within power circuits.

3.1 Core Routing Rules

Rule 1: Separate Power and Signal Traces (Create "Keepout Zones")

Power traces (especially high-current or switching power rails) act as noise sources—keep them away from sensitive signal traces (e.g., analog inputs, I2C/SPI lines) to avoid crosstalk.

Maintain a minimum distance of 3× the width of the wider trace between power and signal traces. For example, a 1mm power trace and 0.2mm analog trace should be ≥3mm apart.

Define "power zones" and "signal zones" on the PCB: route all power traces (input, output, ground) in the power zone; route analog/digital signals in the signal zone. Use a ground plane as a barrier between zones (see Rule 3).